Many electronic devices that are supplied with a commercial alternate current power source (from AC 100 V to AC 240 V) use a switching power supply circuit to obtain a direct current power that drives an inside electronic circuit. Thus, the switching power supply circuit requires a rectifying circuit that converts a commercial alternate current power source into a direct current power source.
When a power factor correction is not performed, current flows through a smoothing capacitor connected posterior to the rectifying circuit only when an input voltage reaches around a peak at which the input voltage exceeds the voltage of the smoothing capacitor. Thus, there has been a problem in which a high-frequency current component occurs in the rectifying circuit to become a high-frequency noise source and a power factor decreases.
The power factor is a value obtained by dividing an input effective power Pi (W) that is a time average of a product of an input voltage and an input current in an alternate current circuit by an apparent power (a product of an effective value of the input voltage and an effective value of the input current), and an effective power is obtained by multiplying the apparent power by a coefficient (the power factor) determined according to a load.
When a load resistance is just added to AC 100 V, a voltage waveform and a current waveform are in phase and the power factor is one.
However, in a switching power supply, a phase of current is shifted with respect to a phase of voltage when there is a load factor such as a capacitor or a choke coil in addition to resistance.
In this case, it is necessary to increase an input current in order to compensate for a decrease in the power factor with respect to the shift, which results in increasing a power loss of an input line such an electric line.
Thus, it is necessary to prevent a decrease in the power factor by use of a power factor correction circuit, so as to reduce the power loss and suppress the high-frequency noise described above.
Non Patent Document 1 listed below discloses a PFC (power factor correction) circuit that includes an error amplifier detecting an output voltage, comparing it with a reference voltage, and amplifying it, and uses a so-called on-time fixing control (a constant on-time control) that controls an on-time width of a switching element to be a certain length according to an output of the error amplifier with respect to a certain load.
FIG. 1 is a diagram that illustrates a configuration of a switching power supply apparatus having the conventional PFC circuit disclosed in Non Patent Document 1 listed below. FIG. 2 illustrates an operational waveform of the conventional power factor correction circuit of FIG. 1.
The PFC circuit of FIG. 1 has a configuration of a boost converter, and when the MOSFET (metal oxide semiconductor field effect transistor) (Q1) 220 that is a switching element is turned on, current IL1 of an inductor (L1) 232 increases from zero, based on a current supplied from an AC source 222 via a rectifying circuit 224.
At the same time, an output Vramp (a carrier signal) of a ramp oscillator (RAMP OSC) 214 within a control IC (integrated circuit) 200 increases with a slope that is determined according to a resistance value of a resistor external to an RT terminal.
Then, a comparator (PWM.comp) 213 compares the output Vramp of the ramp oscillator (RAMP OSC) 214 with an output Vcomp (212) of an error amplifier (ERRAMP) 210, and the MOSFET Q1 (220) is turned off when Vramp>Vcomp, which results in reducing the output Vramp of the ramp oscillator (RAMP OSC) 214.
When the MOSFET Q1 (220) is turned off, a voltage across the inductor L1 (232) is inverted, and the current IL1 of the inductor L1 (232) decreases while supplying current toward an output voltage 236 through a diode D1 (234).
A current comparator 215 detects, on the basis of voltage 216 in an IS terminal, a timing at which the current IL1 of the inductor L1 (232) becomes zero. Then, the MOSFET Q1 (220) is turned on after a delay time, represented by the delay block 273, that is determined according to a resistance value of a resistor external to an RTZC terminal, and the state moves on to the next switching cycle.
This will further be described below. When the MOSFET Q1 (220) is turned on just after zero current is detected, a switching loss increases because it is turned on in a state in which a Vds voltage (voltage between a drain and a source) of the MOSFET Q1 (220) is high. However, if a delay circuit of FIG. 1 is used to delay the next on timing, the Vds voltage decreases due to a resonant operation of parasitic capacitance (not shown) of the MOSFET Q1 (220) and the inductor L1 (232), which permits the MOSFET Q1 (220) to be turned on at an appropriate timing. As a result, the switching loss can be reduced. The control IC 200 has this operation performed repeatedly so as to continue an operation (a critical operation).
In the switching operation described above, when a load of the PFC circuit is constant, a value of the output Vcomp (212) of the error amplifier (ERRAMP) 210 is constant and an on-time width of the MOSFET Q1 (220) is constant. In this case, a peak current of the inductor L1 (232) is obtained using the following formula:Imax=(Vin/L)*ton wherein Imax is a peak current of the inductor L1, Vin is an input voltage, L is an inductance value of the inductor L1, and ton is an on-time width.
In the description above, the peak current Imax of L1 (232) is proportional to Vin (an input voltage) 230 because L and ton are constant. The peak current Imax has an AC (alternate current) waveform that is the same as the input voltage 230, and this operation permits a power factor correction.
In this control scheme that is generally called an “on-time fixing control (a constant on-time control)”, there is no need to detect an input voltage, which provides the advantage of more greatly reducing power consumption than when applying a previous control scheme in which an input voltage is detected by an input voltage detection resistor during a standby period of time.
The operation of the PFC circuit of FIG. 1 that has a configuration of a boost converter will be described. The output voltage 236 of the PFC is divided by voltage division resistors R1 (237) and R2 (238) and input into an FB terminal of the control IC 200. The error amplifier (ERRAMP) 210 outputs the current according to the difference between voltage obtained by the voltage division and 2.5 V, which is a direct current voltage of a reference voltage source 211 included in the control IC 200 (the error amplifier (ERRAMP) 210 being constituted of a transconductance amplifier), and a capacitor 261 that is connected to an output terminal of the error amplifier (ERRAMP) 210 integrates and smooths the output of the error amplifier (ERRAMP) 210, so as to generate a signal Vcomp (212).
Using the signal Vcomp (212), which is an output of the error amplifier (ERRAMP) 210, the control IC 200 controls the switching operation of the MOSFET Q1 (220) such that the output voltage 236 of the PFC circuit is constant (such that the voltage obtained by dividing the output voltage 236 is equal to the 2.5 V that is a direct current voltage of the reference voltage source 211).
On the other hand, the output voltage 236 of the PFC circuit generally includes a ripple component that is synchronized with an AC (alternate current) input 222 based on a commercial power source. When the ripple component appears in the output Vcomp (212) of the error amplifier (ERRAMP) 210, the PFC circuit does not operate stably.
Thus, a phase compensation circuit 262 of a CR (capacitor and resistor) that is connected to a COMP terminal that is also an output of the error amplifier (ERRAMP) 210 is used to cut a bandwidth of a frequency that is higher than twice an input frequency (to drop gain in the bandwidth below 0 dB). As a result, the voltage of the COMP terminal that is also an output of the error amplifier (ERRAMP) 210 is substantially a direct current voltage in a steady state.
Then, the comparator (PWM.comp) 213 within the control IC 200 compares the output Vcomp (212) of the error amplifier (ERRAMP) 210 with the output Vramp of the ramp oscillator (RAMP OSC) 214, a comparison result is output OR gate circuit 275. OR gate circuit 275 is output reset terminal of RS flip-flop (RSFF) 271, then output terminal Q of RS flip-flop (RSFF) 271 is high level. Accordingly AND gate circuit 272 is high level, then AND gate circuit 272 is output high level and consequently the control IC 200 is output from an OUT terminal 217 to a gate of a switching element Q1 (220), and the output voltage 236 of the PFC circuit is adjusted by controlling an on-time width of the switching element Q1 (220).
The PFC circuit illustrated in FIG. 1 is configured to be used in a critical mode in which a switching frequency is low in a heavily loaded state and is high in a lightly loaded state, but a switching pulse continues to be output from the OUT (output) terminal 217 when the state moves from a lightly loaded state to a heavily loaded state (see the OUT waveform of FIG. 2). Thus, there has been a problem in which a switching loss of the MOSFET Q1 (220) increases if the load is lighter, which results in decreasing efficiency.
Further, Patent Document 1 listed below discloses a switching power supply apparatus including a power factor correction circuit that is connected to an alternate current power source and obtains a direct current voltage, and a DC-DC converter that inputs the direct current voltage of the power factor correction circuit into a primary winding of a transformer and converts it into another direct current voltage by having a switching element turning on/off so that a switching frequency is reduced or the state moves on to an intermittent oscillation in an unloaded or lightly loaded state, wherein the switching power supply apparatus includes a first rectifying and smoothing circuit that rectifies a voltage occurring in a second winding of the transformer, smooths it by use of a first smoothing capacitor, and provides it to a load, a second rectifying and smoothing circuit that rectifies a voltage occurring in a control winding of the transformer and smooths it by use of a second smoothing capacitor, and a light-load detection circuit that determines that a switching frequency has been reduced or the state has moved on to an intermittent oscillation when detecting that an output ripple of the first rectifying and smoothing circuit is not less than a predetermined value and that stops the power factor correction circuit.
Patent Document 1 teaches that the switching power supply apparatus determines that a switching frequency has been reduced or the state has moved on to an intermittent oscillation when detecting that an output ripple of the second rectifying and smoothing circuit is not less than a predetermined value, and stops the power factor correction circuit, which permits a reduction in standby power consumption.
In particular, in Patent Document 1, a control IC 72 of the DC-DC converter enters a standby operation mode in a lightly loaded state, and a switching element Q2 performs an intermittent oscillation at a frequency that is much lower than a switching frequency in a normal mode (interval t1-t7 in FIG. 6 of Patent Document 1). In this case, voltage VC5 of a smoothing capacitor C5 that corresponds to the above-described first smoothing capacitor is controlled to be substantially constant either in a heavily loaded state or in a lightly loaded state. On the other hand, when it enters a lightly loaded state, the switching element Q2 performs an intermittent oscillation at a frequency that is much lower than a switching frequency in a normal mode, so voltage VC4 of a smoothing capacitor C4 that corresponds to the above-described second smoothing capacitor is discharged by a time constant depending on the smoothing capacitor C4 and its load impedance (an impedance of a light-load detection circuit 15) and then decreases during a non-oscillation time period (interval t1-t3 and interval t5-t7 in FIG. 6 of Patent Document 1), which results in causing a large ripple.
The light-load detection circuit 15 compares a reference voltage Vref with the voltage Vc4 of the smoothing capacitor C4, and when the voltage Vc4 of the smoothing capacitor C4 is not greater than the reference voltage Vref (interval t2-t4 and interval t6-t8 in FIG. 6 of Patent Document 1), it outputs a voltage signal Vse1 to a PFC control circuit 6a and stops the PFC control circuit 6a. Thus, it is possible to stop a power factor correction circuit 5 for almost all the time period for which an intermittent oscillation is performed. Further, for the time period for which an intermittent oscillation is performed (t1-t7 in FIG. 6 of Patent Document 1), when a time period within the light-load detection circuit 15 is made greater such that the voltage Vc4 of the smoothing capacitor C4 does not increase until it reaches the reference voltage Vref, a signal that is output from the light-load detection circuit 15 to the PFC control circuit 6a is like a voltage signal Vse2 illustrated in FIG. 6 of Patent Document 1, and it is possible to continue to stop the power factor correction circuit 5 for the time period for which a discrete time oscillation is performed. Therefore, according to the switching power supply apparatus in the sample, the light-load detection circuit 15 determines that the state has moved on to an intermittent oscillation when detecting that an output ripple of the smooth capacitor C4 is not less than a predetermined value, and stops the PFC control circuit 6a, which makes it possible to easily determine from the outside that the DC-DC converter has moved on to a standby operation and stop the power factor correction circuit 5 with certainty so as to reduce standby power consumption.    Patent Document 1: Japanese Laid-open Patent Publication No. 2005-348560    Non Patent Document 1: Takato Sugawara and two others, “<FA5590 Series> of 2nd Generation Critical Mode PFC Control ICs”, Fuji Jiho, Fuji Electric Co., Ltd., Nov. 10, 2010, Vol. 83 No. 6, p. 405-410